RELEASED
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
Bits
Description (Continued)
CRC Action. This specifies what action is to be taken when an enabled port (port enable
register bit is 1) encounters a CRC error from its attached Port Processor. If set to 0 then the
port with the error is shut down and the Scheduler continues to arbitrate among the remaining
ports. If set to 1 then the Scheduler will reset all serial links, effectively disabling all 32 ports.
This bit should only be set to 1 for the primary Scheduler within a core with redundant
Schedulers.
2
Subport mode. If set to 1 then the Scheduler operates in subport mode, in which each port is
considered to be four subports with only one priority. This bit is not used in the ETT1 Scheduler
and must be set to 0.
1
0
Reset. Writing a 1 to this location will reset the entire device. It is equivalent to a hardware
reset. This register is cleared automatically when the chip is reset. This bit will always read as 0
and it is not necessary to write a 0 having just written a 1. Soft reset takes 1mS to complete.
5.4.2.3 Low Priority Mask
Symbol: SIRLMSK
Address Offset: 00008h
Default Value: 00000000h
Access:
Read/Write
Interrupt Mask for interrupts.
Bits
Description
31:5
4:0
Reserved.
Low Priority Mask. Mask bits for low priority interrupts. Each mask bit is set to 1 to enable a
low priority interrupt when the corresponding bit in the Status Register is 1.
5.4.2.4 High Priority Mask
Symbol: SIRHMSK
Address Offset: 0000Ch
Default Value: 00000000h
Access:
Read/Write
Interrupt Mask for interrupts.
Bits
Description
31:5
Reserved.
262
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
PMC [ PMC-SIERRA, INC ]
