RELEASED
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
5.4.2 Scheduler Register Descriptions
Read and Clear means that reading the register causes it to be cleared (reset to zero).
All bits labled as Reserved should be set to 0.
5.4.2.1 Status
Symbol:
SSTS
Address Offset: 00000h
Default Value: 30000000h
Access:
Read Only
Status register.
Bits
Description
31:28 Chip ID Number. Identifies the specific device.
27:24 Chip Revision Number.
23:2
Reserved.
High Priority Interrupt. 1 = an outstanding high priority interrupt. One of the bits in the
Interrupt Register is set, and is enabled via its corresponding high priority mask.
1
Low Priority Interrupt. 1 = an outstanding low priority interrupt. One of the bits in the Interrupt
Register is set, and is enabled via its corresponding low priority mask.
0
5.4.2.2 Control and Reset
Symbol: SCTRLRS
Address Offset: 00004h
Default Value: 00000130h
Access:
Read/Write
Control and Reset register.
Bits
Description
31-9 Reserved.
BP_FIFO. Specifies the depth of the backpressure FIFO. This is an internal FIFO and users
should set these bits to a value of 14h after reset. The default value is 13h
8-4
3
Reserved.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
261
PMC [ PMC-SIERRA, INC ]
