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PM9315-HC 参数 Datasheet PDF下载

PM9315-HC图片预览
型号: PM9315-HC
PDF下载: 下载PDF文件 查看货源
内容描述: 增强TT1 ™交换机结构 [ENHANCED TT1⑩ SWITCH FABRIC]
分类和应用: 电信集成电路电信电路
文件页数/大小: 343 页 / 5229 K
品牌: PMC [ PMC-SIERRA, INC ]
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RELEASED  
PMC-Sierra, Inc.  
PM9311/2/3/5 ETT1™ CHIP SET  
Data Sheet  
PMC-2000164  
ISSUE 3  
ENHANCED TT1™ SWITCH FABRIC  
Bits  
Description  
High Priority Mask. Mask bits for high priority interrupts. Each mask bit is set to 1 to enable a  
high priority interrupt when the corresponding bit in the Status Register is 1.  
4:0  
5.4.2.5 Interrupt Register  
Symbol: SIR  
Address Offset: 00010h  
Default Value: 00000000h  
Access:  
Read and Clear  
Interrupt Register.  
Bits  
Description  
31:5  
Reserved.  
All Ports Refreshed. During a refresh operation, this bit will be set when all enabled ports  
have been refreshed. See also Refreshed Status register. This bit is cleared on reading this  
register.  
4
TDM Sync Lost. This bit is set if the TDM feature has been configured, and no Sync signal is  
received for three consecutive sync periods. This would suggest that a failure has occurred in  
either the Port Processor or its attached linecard. This bit is cleared on reading this register.  
3
2
Ready Inactive. This is the logical OR of the Link Ready Inactive Interrupt register, after it has  
been masked by the Link Ready Inactive Interrupt Mask register. This bit is set if a serial link  
goes from active to inactive and the corresponding mask bit is 1. This bit is not cleared when  
read - the user must clear the Link Ready Inactive Interrupt register.  
Ready Active. This is the logical OR of the Ready Active interrupt register, after it has been  
masked. This is set if a serial link goes from inactive to active and the corresponding mask bit is  
1. This bit is not cleared when read - the user must clear the Ready Active interrupt register.  
1
0
CRC Error. This is the logical OR of the CRC interrupt register, after it has been masked. This  
is set if a CRC error occurs and the corresponding mask bit is 1. This bit is not cleared when  
read - you must clear the CRC register.  
5.4.2.6 CRC Error Interrupt Mask  
Symbol: SCRCMSK  
Address Offset: 00014h  
Default Value: 00000000h  
Access:  
Read/Write  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
263  
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