RELEASED
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
5.4 SCHEDULER REGISTERS
The Scheduler device select low-order bits are hard wired on the board by four pins (oobdev_sel[3:0]) on
the Scheduler package. See Section 1.7.1.3 “Individual Device Selects” on page 79 for more information.
5.4.1 Summary
The following table is a summary of information for all registers in the Scheduler. See the following
Descriptions section for more information on individual registers.
Read and Clear means that reading the register causes it to be cleared (reset to zero)
Table 36. Scheduler Register Summary
Default
Value
Address
Access
Register
Symbol
SSTS
00000h
00004h
00008h
0000Ch
Read Only
Read/Write
Read/Write
Read/Write
Status
00000000h
00000130h
00000000h
00000000h
Control and Reset
Low Priority Mask
High Priority Mask
SCTRLRS
SIRLMSK
SIRHMSK
Read and
Clear
00010h
00014h
00018h
0001Ch
00020h
00024h
00028h
Interrupt Register
SIR
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
Read/Write
CRC Error Interrupt Mask
CRC Errors
SCRCMSK
SCRC
Read and
Clear
Read/Write
Link Ready Inactive Interrupt Mask
Link Ready Inactive
SRDYDMSK
SRDYDN
SRDYUMSK
SRDYUP
Read and
Clear
Read/Write
Link Ready Active Interrupt Mask
Link Ready Active
Read and
Clear
00030h
00034h
00038h
0003C
Read/Write
Read Only
Read/Write
Read/Write
Read/Write
AIB Reset
SAIBRS
FFFFFFFFh
00000000h
00000000h
00000000h
00000000h
AIB Ready
SAIBRDY
SENBPRT
SPORTEN
FCCSYN
Enable Port
AIB Tx Enable
Flow Control Crossbar Sync
00040h
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
259
PMC [ PMC-SIERRA, INC ]
