RELEASED
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
5.4.2.9 Link Ready Inactive
Symbol:
SRDYDN
Address Offset: 00020h
Default Value: 00000000h
Access:
Read and Clear
Each bit indicates if the Ready signal from a link has transitioned from Active to Inactive (the link has gone
down for some reason).
NOTE: The link may be up again (active) by the time the CPU reads this register. Mask off
unwanted (unused ports) bits via the Link Ready Inactive Interrupt Mask. Reading this
register will clear all bits.
Bits
Description
Link Ready Inactive. Each bit indicates if the Ready signal from a link has transitioned from
Active to Inactive.
31:0
5.4.2.10 Link Ready Active Interrupt Mask
Symbol: SRDYUMSK
Address Offset: 00024h
Default Value: 00000000h
Access:
Read/Write
Enables interrupts when the corresponding bit in the Link Ready Active register is set to 1.
Bits
Description
Link Ready Active Interrupt Mask. Each bit is used to mask (enable) interrupts when the
corresponding bit in the Link Ready Active register is set to 1. The interrupt is enabled when the
bit is 1.
31:0
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
265
PMC [ PMC-SIERRA, INC ]
