RELEASED
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
•
The appropriate register (CRC or Link Ready Inactive) is updated.
This port asserts backpressure to all other ports. Once the CPU determines that this port can continue
operation, then a refresh operation must be performed on this port and then the port can be enabled.
If the CRC_Action bit is set, then in addition to the above actions, the Scheduler also asserts reset to all of
its serial links to all EPPs. This turns off all of the links, forcing all of the EPPs to switch to the secondary
Scheduler. All of the primary Scheduler’s ports are set to the disabled state and the enable_port register is
set to 0.
The Scheduler must be reset by the CPU and have its queue information refreshed before it is re-enabled.
258
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
PMC [ PMC-SIERRA, INC ]
