RELEASED
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
Interrupt mask for CRC errors.
Bits
Description
CRC Error Interrupt Mask. Each bit is used to mask (enable) interrupts when the
corresponding bit in the CRC Error register is set to 1. The interrupt is enabled when the bit is 1.
31:0
5.4.2.7 CRC Errors
Symbol: SCRC
Address Offset: 00018h
Default Value: 00000000h
Access:
Read and Clear
CRC Interrupt Error Register
Bits
Description
CRC Errors. Each bit indicates if a CRC error has occurred on the appropriate link (Port
Processor to Scheduler) since the last time this register was read. Mask off unwanted (unused
ports) bits via the CRC Error Interrupt Mask.
31:0
5.4.2.8 Link Ready Inactive Interrupt Mask
Symbol: SRDYDMSK
Address Offset: 0001Ch
Default Value: 00000000h
Access:
Read/Write
Enables interrupts when the corresponding bit in the Link Ready Inactive register is set to 1.
Bits
Description
Link Ready Inactive Interrupt Mask. Each bit is used to mask (enable) interrupts when the
corresponding bit in the Link Ready Inactive register is set to 1. The interrupt is enabled when
the bit is 1.
31:0
264
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
PMC [ PMC-SIERRA, INC ]
