PRELIMINARY
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
Table 24. Enhanced Port Processor Register Summary (Continued)
Default
Value
Address
Symbol
EAIBEN
Register
Access
0003Ch
00040h
AIB Enable Transmitter
Read/Write
Read/Write
00000000h
00000000h
ELCSSSS
ELGCBD
LCS Started/Stopped Status/Control
Read and
Clear
00044h
00048h
0004Ch
00050h
00054h
00058h
0005Ch
00060h
00064h
00068h
0006Ch
00070h
00074h
00078h
0007Ch
Lost Grant or Cell Body Debug Info
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
Scheduler Grant to Empty Queue Debug
Info
Read and
Clear
ESGEQD
ELCSECT
ELCSP0CT
ELCSP1EC
ELCSP2EC
ELCSP3EC
EIS0VCT
Read and
Clear
LCS Header CRC Error Count
LCS Processor CP Subport 0 CRC Error
Count
Read and
Clear
LCS Processor CP Subport 1 CRC Error
Count
Read and
Clear
LCS Processor CP Subport 2 CRC Error
Count
Read and
Clear
LCS Processor CP Subport 3 CRC Error
Count
Read and
Clear
Read and
Clear
Input Subport 0 Valid Count
Input Subport 1 Valid Count
Input Subport 2 Valid Count
Input Subport 3 Valid Count
Output Subport 0 Valid Count
Output Subport 1 Valid Count
Output Subport 2 Valid Count
Output Subport 3 Valid Count
Read and
Clear
EIS1VCT
Read and
Clear
EIS2VCT
Read and
Clear
EIS3VCT
Read and
Clear
EOS0VCT
EOS1VCT
EOS2VCT
EOS3VCT
Read and
Clear
Read and
Clear
Read and
Clear
166
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
PMC [ PMC-SIERRA, INC ]
