Released
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
3.4 ENHANCED PORT PROCESSOR REGISTERS
The Enhanced Port Processor device select low-order bits are hard wired on the board by four pins
(oobdev_sel[3:0]) on the Enhanced Port Processor package. See section 1.7.1.3 “Individual Device
Selects” on page 79 for more information.
3.4.1 Enhanced Port Processor Summary
The following table is a summary of information for all registers in the Enhanced Port Processor. See the
following Descriptions section for more information on individual registers.
Read and Clear means that reading the register causes it to be cleared (reset to zero).
Table 24. Enhanced Port Processor Register Summary
Default
Value
Address
00000h
Symbol
ESTS
Register
Access
Status
Read Only
Read/Write
Read/Write
Read/Write
51000000h
00000031h
00000000h
00000000h
00004h
00008h
0000Ch
ETKNRS
EIRLMSK
EIRHMSK
Reset and Control
Low Priority Mask
High Priority Mask
Read and
Clear
00010h
EIR
Interrupt Register
00000000h
00014h
00018h
ELPAIBIM
EHPAIBM
Low Priority AIB Interrupt Mask
High Priority AIB Interrupt Mask
Read/Write
Read/Write
00000000h
00000000h
Read and
Clear
0001Ch
00020h
00024h
00028h
EAIBIR
ELPICIR
EHPICIR
EIICIR
AIB Interrupt Register
00000000h
00000000h
00000000h
00000000h
Low Priority Incremental Credit Interrupt
Mask
Read/Write
Read/Write
High Priority Incremental Credit Interrupt
Mask
Invalid Incremental Credit Interrupt
Register
Read and
Clear
00030h
00034h
00038h
EAIBRS
EAIBRDY
EEN
AIB Reset
Read/Write
Read Only
Read/Write
0000003Fh
00000000h
00000000h
AIB Ready
Enable Port Processor
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
165
PMC [ PMC-SIERRA, INC ]
