PRELIMINARY
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
customer’s implementation. The CPU Control Packet locations should be written whenever the customer’s
software is about to send a CPU control packet to the linecard. The given locations for the other types of
Control Packets must be initialized after the Dataslices are reset and before traffic is sent through the
switch.
Table 23. EPP Egress Control Packet Data Format and Dataslice OOB Addressing
OOB Address
Control Packet Type
DS0
(msb) 0x70F00 0x0000
DS1
0x0031
DS2
DS3...DS11
Offset
CPU (CRC-16
header mode)
(lsb) 0x70F04
0x00000010
(msb) 0x70F00 0x0000
0x0057
CPU (CRC-8
header mode)
(lsb) 0x70F04
0x00000010
(msb) 0x70F10 0x0000
0x0000
0x0000
LCS Stop
(lsb) 0x70F14
0x00000000
0x02000000
0x0000
0x00006E9F
0x0000
(msb) 0x70F18 0x0000
LCS Start
(lsb) 0x70F1C
0x00000000
0x02800000
0x0000
0x0000C566
0x0000
(msb) 0x70F20 0x0000
TDM Sync Sel 0
TDM Sync Sel 1
(lsb) 0x70F24
0x00000000
0x00000000
0x0000
0x0000E139
0x0000
(msb) 0x70F28 0x0000
(lsb) 0x70F2C
0x00000000
0x00800000
0x00004AC0
164
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
PMC [ PMC-SIERRA, INC ]
