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PM9315-HC 参数 Datasheet PDF下载

PM9315-HC图片预览
型号: PM9315-HC
PDF下载: 下载PDF文件 查看货源
内容描述: 增强TT1 ™交换机结构 [ENHANCED TT1⑩ SWITCH FABRIC]
分类和应用: 电信集成电路电信电路
文件页数/大小: 343 页 / 5229 K
品牌: PMC [ PMC-SIERRA, INC ]
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Released  
PMC-Sierra, Inc.  
PM9311/2/3/5 ETT1™ CHIP SET  
Data Sheet  
PMC-2000164  
ISSUE 3  
ENHANCED TT1™ SWITCH FABRIC  
3.4.2 Enhanced Port Processor Register Descriptions  
Read and Clear means that reading the register causes it to be cleared (reset to zero).  
All bits labeled as Reserved should be set to 0.  
3.4.2.1 Status  
Symbol:  
ESTS  
Address Offset: 00000h  
Default Value: 51000000h  
Access:  
Read Only  
Bits  
Description  
31:28 Chip ID Number. Identifies the specific ETT1 device.  
27:24 Chip Revision Number.  
23:2  
Reserved.  
High Priority Interrupt. 1 = an outstanding high priority interrupt. One of the bits in the  
Interrupt Register is set, and is enabled via its corresponding high priority mask.  
1
Low Priority Interrupt. 1 = an outstanding low priority interrupt. One of the bits in the Interrupt  
Register is set, and is enabled via its corresponding low priority mask.  
0
3.4.2.2 Reset and Control  
Symbol: ETKNRS  
Address Offset: 00004h  
Default Value: 00000031h  
Access:  
Read/Write  
Reset and Control register.  
Bits  
Description  
31-15  
14  
Reserved.  
13th and 14th Dataslice Enable. This bit must be set before bringing up the Dataslices’  
fiber-optics links in systems that use 14 Dataslices. Note: This bit will read out in bit position 6.  
13:6  
Reserved  
Generate Truncated 16-bit CRC. For Switch to Linecard LCS headers, generate a 16-bit  
CRC (0x11021) over the header, but only send the lower 8 bits, if this bit is 1. If this bit is 0,  
generate an 8-bit CRC (0x107) over the header and send that.  
5
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
169  
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