Released
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
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Set Fault Tolerance Control
Enable Port Processor
Define 1-in-N Idle Count value
Take EPP out of LCS Stop mode
When Crossbar AIB ready up:
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Inform local processes that the Crossbar is operational
Enable all interrupts on Crossbar
When Scheduler AIB ready up:
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Inform local processes that the Scheduler is operational
Enable all interrupts on Scheduler
Enable ports that are present and up
Enable non-TDM traffic
If TDM traffic, define TDM control and Enable TDM traffic
In a system with redundant Schedulers, it is essential to perform a refresh operation as the final step, once
ports are configured and operational. This synchronizes the two Schedulers. Refresh schedulers if
necessary (do not refresh if only one in system)
1.8.2 Port Board being added:
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Wait for voltage ramp-up
Suggested:
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Initialize the OOB satellite FPGA
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If a Scheduler is present and has its Control register's CRC Action bit set, save and clear the CRC
Action bit.
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Reset Enhanced Port Processor
Reset Dataslices
Enable PLLs on EPP and DSs (turn off PLL reset)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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PMC [ PMC-SIERRA, INC ]
