Released
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
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Initialize the OOB satellite FPGA
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Reset Crossbar
Enable PLLs on Crossbar (turn off PLL reset)
Set interrupt masks (disable all except ready up)
If neighboring Port cards are present and this is a Flow Control Crossbar:
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Reset EPP AIB and Flow Control Crossbar AIB (for all ports present)
Enable EPP AIB and Flow Control Crossbar AIB (for all ports present)
Release reset on EPP AIB and Flow Control Crossbar AIB (for all ports present)
If neighboring Port cards are present and this is a data Crossbar:
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•
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Reset DS AIB and Crossbar AIB (for all ports present)
Enable DS AIB and Crossbar AIB (for all ports present)
Release reset on DS AIB and Crossbar AIB (for all ports present)
These sequences should complete with only the "ready up" interrupts enabled. When these interrupts
occur (which may be during later parts of the above sequences) then perform the following:
When Crossbar AIB ready up:
•
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Inform local processes that the Crossbar is operational
Enable all interrupts on Crossbar
1.9 FAULT TOLERANCE
A ETT1 fabric can optionally be configured with redundant elements. When the ETT1 system contains
redundant Schedulers and Crossbars, it is capable of sustaining certain faults and yet not lose or corrupt
any of the cells within the fabric.
1.9.1 Fault Tolerance Model
The fault tolerance model assumes that any failure within a redundant element will manifest itself as a link
error, and thus will be observable by the local CPU. The redundant elements are the Scheduler and
Crossbar which are connected via AIB links to the Enhanced Port Processor and Dataslice, as shown in
Figure 39. These AIB links are protected by a CRC such that a failure in a device will likely result in a CRC
error, which can be detected by the local CPU through interrupts. Furthermore, even if a CRC error is not
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
91
PMC [ PMC-SIERRA, INC ]
