Released
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
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Enable DS 8b10b decoder
Suggested:
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disable Serdes clock phase shifting when sync is established
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Set Scheduler BP depth field of Control register to 0x14.
Set Scheduler action bits (Configuration dependent. See "Enhanced Port Processor - Scheduler"
on page 83)
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Enable the Flow Control Crossbar sync from the Scheduler
Reset DS AIB (for all ports present)
Reset Crossbar AIB (for all ports present)(includes Flow Control Crossbars)
Reset EPP AIB (for all ports present)
Reset Scheduler AIB (for all ports present)
Enable DS AIB (for all ports present)
Enable Crossbar AIB (for all ports present)(includes Flow Control Crossbars)
Release reset on DS AIB
Release reset on Crossbar AIB
Release reset on EPP AIB
Release reset on Scheduler AIB
These sequences should complete with only the "ready up" interrupts enabled. When these interrupts
occur (which may be during later parts of the above sequences) then perform the following:
When DS AIB ready up:
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Inform local processes that the DS is operational
Enable all interrupts on DS, except for Transceiver Comma Detect and 8b10b Decoder Comma
Detect which are set every time an idle is received.
When EPP AIB ready up for at least one Scheduler and at least one set of Flow Control Crossbars:
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Inform local processes that the EPP is operational
Enable all interrupts on EPP
86
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
PMC [ PMC-SIERRA, INC ]
