Released
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
The bus master must clear an interrupt by reading an appropriate register within the device that has
asserted the interrupt.
Figure 38. Interrupts are Active High and Synchronous
CLK
INT_HI
INT_LO
Bus Rules
1. The target slave must assert WAIT_L during the final address cycle. If the master does not see
WAIT_L asserted during the final address cycle then it concludes that there is no device at that
address and terminates the cycle (takes VALID_L high).
2. VALID_L must be de-asserted (high) for at least one clock cycle between accesses. The master
must drive the board address on AD[6:0] during a positive clock edge while VALID_L is
de-asserted (high).
3. A slave may insert up to 255 wait states before it must de-assert WAIT_L. Failure to de-assert
WAIT_L within that time will result in a Bus Error. (The master will terminate the cycle by
de-asserting VALID_L)
1.8 INITIALIZATION PROCEDURE
Every ETT1 component must be correctly initialized before being used within a switch system. In general,
the process of initialization depends on whether the whole switch is being initialized (initial power-on
sequence) or whether a component is being added to a switch system that is already operating. However,
to simplify the process, this document describes an initialization sequence that can be used in either case,
but does incur some redundant operations when used at system initialization.
The initialization sequence is also a function of the physical organization of the ETT1 devices. The
sequence described here assumes the physical configuration that has been used in the ETT1 Reference
System: each port board has one Enhanced Port Processor and six or seven Dataslice devices; each
Crossbar board has two Crossbar devices; each Scheduler board has one Scheduler device. The system
has redundant Crossbars and Schedulers. The link between the linecards and the ETT1 ports uses
industry standard Serdes devices.
NOTE: For more information on the link synchronization involving the Serdes and the fiber optics,
see Appendix C, Section 2 “The 8b/10b Interface to the Dataslice” on page 328.
84
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
PMC [ PMC-SIERRA, INC ]
