Released
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
keeps WAIT_L asserted through bus turn-around cycle (effectively a wait cycle). The target de-asserts
WAIT_L once the first valid data byte is on the bus. VALID_L must be high for at least two rising clocks
before the next cycle. There is an additional bus turn-around cycle during the Recover cycle. This is the
fastest read cycle: there is always at least one bus turn-around cycle whenever AD is tri-stated. The
master must drive the AD signals before the next rising edge of the clock after the VALID_L is deasserted.
Figure 36. Read Cycle - One Wait
Wt
D0
D1
D2
D3
Rec
Idle
A0
A1
A2
A3
CLK
AD[7]
AD[6:0]
a23
a15
a7
d31
d30:24
d23
d15
d7
d6:0
W/R
board
board
address
a30:24
a22:16 a14:8
a6:0
d22:16 d14:8
address
VALID_L
WAIT_L
1.7.1.9 A Read Cycle - Two Waits
This is the same as a single wait read cycle except that there is an extra wait cycle before D31:24 are valid
and WAIT_L is de-asserted.
Figure 37. Read Cycle - Two Waits
Wt
Idle
A0
A1
A2
A3
Wt
D0
D1
D2
D3
Rec
CLK
AD[7]
AD[6:0]
a23
a15
a7
a6:0
d31
d23
d15
d7
d6:0
W/R
a30:24
board
board
address
a22:16 a14:8
d30:24 d22:16 d14:8
address
VALID_L
WAIT_L
1.7.1.10 Interrupts
Two active high interrupt lines are provided. INT_HI is for “emergency” interrupts such as a card failing.
INT_LO is for non-emergency interrupts such as a device requesting to be polled for some reason.
Interrupts are asserted and de-asserted synchronously with respect to the clock. Interrupts can be
asserted at any time, even during an access.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
83
PMC [ PMC-SIERRA, INC ]
