Released
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
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Reset Scheduler
Enable PLLs on SCH (turn off PLL reset)
Set BP depth field of Control register to 0x14.
Set Scheduler action bits (Configuration dependent. See "Enhanced Port Processor - Scheduler"
on page 83)
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Enable the Flow Control Crossbar sync
Set interrupt masks (disable all expect ready up)
If neighboring Port cards are present:
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Reset EPP AIB and Scheduler AIB (for all ports present)
Enable EPP AIB and Scheduler AIB (for all ports present)
Release reset on EPP AIB and Scheduler AIB (for all ports present)
Reset ports on Scheduler
These sequences should complete with only the "ready up" interrupts enabled. When these interrupts
occur (which may be during later parts of the above sequences) then perform the following:
When Scheduler AIB ready up:
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Inform local processes that the Scheduler is operational
Enable all interrupts on Scheduler
Enable ports that are present and up
Enable non-TDM traffic
If TDM traffic, define TDM control and Enable TDM traffic
In a system with redundant Schedulers, it is essential to perform a refresh operation as the final step, once
ports are configured and operational. This synchronizes the two Schedulers. Refresh schedulers if
necessary (do not refresh if only one in system)
1.8.4 Crossbar Board being added:
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Wait for voltage ramp-up
Suggested:
90
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
PMC [ PMC-SIERRA, INC ]
