Released
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
Figure 34. Write Cycle - No Wait
A0
A1
A2
A3
D0
D1
D2
D3
Rec
Idle
CLK
AD[7]
a23
a15
a7
a6:0
d31
d30:24
d23
d15
d7
d6:0
W/R
a30:24
board
address
AD[6:0]
VALID_L
a22:16 a14:8
d22:16 d14:8
board address
WAIT_L
Addresses are presented during cycles A0-A3. The write data is presented during D0-D3. There is then a
recover cycle during which the target performs the write.
1.7.1.7 A Write Cycle - One Wait
If, during D3, the target decides that it may not be able to complete the write immediately, then it must
assert WAIT_L. It continues to assert WAIT_L until the write is completed or WAIT_L has been asserted for
256 cycles, at which time WAIT_L is de-asserted. (If WAIT_L is asserted for 256 cycles then the master will
consider this to be a bus error).
Figure 35. shows a write cycle with the target forcing a one cycle wait. The target slave asserts WAIT_L
during A3 to indicate that the target is active. The target then de-asserts WAIT_L and re-asserts it during
D3. The master must maintain d7:0 until WAIT_L is de-asserted.
Figure 35. Write Cycle - One Wait
A0
A1
A2
A3
D0
D1
D2
D3
Wt
Rec
CLK
AD[7]
a23
a15
a7
a6:0
d31
d30:24
d23
d15
d7
d6:0
W/R
a30:24
board
address
board
address
AD[6:0]
a22:16 a14:8
d22:16 d14:8
VALID_L
WAIT_L
1.7.1.8 A Read Cycle - One Wait
A simple 32-bit read. The master drives out a 31-bit address, 8 bits at a time, most significant bits first;
AD[7] is driven low in the first cycle to indicate a read cycle. VALID_L is asserted by the master to indicate
the new cycle. The target slave asserts WAIT_L during A3 to indicate that the target is active. The target
82
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
PMC [ PMC-SIERRA, INC ]
