PM7385 FREEDM-84A672
DATA SHEET
PMC-1990114
ISSUE 6
84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
WITH ANY-PHY PACKET INTERFACE
The RVAL and REOP signals indicate the presence and end of valid packet data
respectively. The RERR and RMOD signals are only valid at the end of a packet
and are qualified with the REOP signal. When a packet is errored, the FREEDM-
84A672 may be programmed to overwrite RXDATA[15:0] in the final word of
packet transfer with status information indicating the cause of the error.
RXDATA[15:0] is not modified if a packet is error free.
The RXADDR[2:0] signals serve to poll FREEDM-84A672 devices as well as for
selection. During data transfer, the RXADDR[2:0] signals continue to poll the
FREEDM-84A672 devices sharing the Rx APPI. Polled results are returned on
the RPA signal. Note that each poll address is separated by a NULL address to
generate tristate turn-around cycle in order to prevent multiple FREEDM-84A672
devices from briefly driving RPA. If RPA is a point-to-point signal for each
FREEDM-84A672 device on the board, then the tristate turn-around cycle is not
required, thereby effectively doubling the polling bandwidth at the expense of
extra signals.
Polled results reflect the status of the two FIFOs in the RAPI672. Polled
responses always refer to the next data transfer. In other words, polled
responses during or after the RXCLK cycle where RSX is set high refer to the
FIFO which is not involved in the current data transfer. For example, once FIFO
one begins transferring data on the Rx APPI (RSX set high), any polls against
that FREEDM-84A672 device respond with the status of FIFO two. This allows
the external controller to gather knowledge about the FIFO not involved in the
current data transfer so that it can anticipate reselecting that FREEDM-84A672
device (via RENB) to maximize bandwidth on the Rx APPI (shown in Figure 18).
Figure 17 – Receive APPI Timing (Auto Deselection)
RXCLK
RXADDR[2:0]
RPA
Dev 0
NULL
Dev 7
Dev 0
NULL
CH 2
Dev 6
Dev 7
NULL
Dev 4
D98
NULL
Dev 4
Dev 0
NULL
Dev 0
Dev 3
CH 8
NULL
Dev 2
Dev 3
NULL
Dev 2
RENB
Dev 0
D1
Dev 0
D0
RXDATA[15:0]
RVAL
D0
D99
D1
RSX
REOP
RMOD
RERR
Figure 17 shows the transfer of a 100 word packet across the Rx APPI from
FREEDM-84A672 device 0, channel 2 followed by the transfer of a 2 word packet
from FREEDM-84A672 device 0, channel 8. More importantly, Figure 17
illustrates that, for back-to-back transfers from the same FREEDM-84A672
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
212
PMC [ PMC-SIERRA, INC ]
