PM7385 FREEDM-84A672
DATA SHEET
PMC-1990114
ISSUE 6
84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
WITH ANY-PHY PACKET INTERFACE
12.2 SBI ADD BUS Interface Timing
Figure 13 – DS3 Add Bus Adjustment Request Functional Timing
SSS
REFCLK
SSS
C1FP
SSS
DS-3 #1 DS-3 #2DS-3 #3DS-3 #1
ADATA[7:0]
APL
C1
H3
H3
H3
SSS
SSS
SSS
SSS
SSS
AV5
ADP
AJUST_REQ
AACTIVE
Figure 13 illustrates the operation of the SBI ADD BUS, using positive and
negative justification requests as an example. (The responses to the justification
requests would take effect during the next multi-frame.) The negative justification
request occurs on the DS-3#3 tributary when AJUST_REQ is asserted high
during the H3 octet. The positive justification occurs on the DS-3#2 tributary
when AJUST_REQ is asserted high during the first DS-3#2 octet after the H3
octet. The AACTIVE signal is shown for the case in which FREEDM-84A672 is
only driving DS-3#2 onto the SBI ADD bus.
12.3 Receive Link Timing
The timing relationship of the receive clock (RCLK[n]) and data (RD[n]) signals is
shown in Figure 14. The receive data is viewed as a contiguous serial stream.
There is no concept of time-slots or framing. Every eight bits are grouped
together into a byte with arbitrary alignment. The first bit received (B1 in Figure
14) is deemed the most significant bit of an octet. The last bit received (B8) is
deemed the least significant bit. Bits that are to be processed by the FREEDM-
84A672 are clocked in on the rising edge of RCLK[n]. Bits that should be ignored
(X in Figure 14) are squelched by holding RCLK[n] quiescent. In Figure 14, the
quiescent period is shown to be a low level on RCLK[n]. A high level, effected by
extending the high phase of the previous valid bit, is also acceptable. Selection
of bits for processing is arbitrary and is not subject to any byte alignment nor
frame boundary considerations.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
209
PMC [ PMC-SIERRA, INC ]
