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PM7385 参数 Datasheet PDF下载

PM7385图片预览
型号: PM7385
PDF下载: 下载PDF文件 查看货源
内容描述: 84 LINK , 672通道帧引擎和数据链路管理与ANY -PHY分组接口 [84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER WITH ANY-PHY PACKET INTERFACE]
分类和应用:
文件页数/大小: 244 页 / 2231 K
品牌: PMC [ PMC-SIERRA, INC ]
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PM7385 FREEDM-84A672  
DATA SHEET  
PMC-1990114  
ISSUE 6  
84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER  
WITH ANY-PHY PACKET INTERFACE  
Figure 21 – Transmit APPI Timing (Special Conditions)  
TXCLK  
TRDY  
Dev 3  
Dev 5  
TXDATA[15:0]  
TSX  
CH 0  
D0  
CH 671  
D0  
D1  
D2  
CH 2  
D0  
TEOP  
TMOD  
TERR  
Figure 21 shows two special conditions – (1) the transfer of a one word packet  
illustrating how the external controller must wait until TRDY has been sampled  
high before the next data transfer can begin, and (2) the transfer of a packet  
which completes when TRDY is set low illustrating that although the packet has  
been completely transferred, the external controller must still wait until TRDY has  
been sampled high before the next data transfer can begin.  
The first data transfer is a single word packet for FREEDM-84A672 device 3,  
channel 0. The FREEDM-84A672 asserts TRDY high one TXCLK cycle after  
TSX is sampled high. The Tx APPI protocol dictates that the external controller  
must wait until TRDY is sampled high before beginning the next data transfer for  
FREEDM-84A672 device 5, channel 671. The external controller must hold the  
last valid word on TXDATA[15:0] until TRDY is sampled high. In this case, that  
data is a don’t care. The FREEDM-84A672 tristates the TRDY signal one TXCLK  
cycle after it has been driven high.  
The second transfer is a three word packet which completes transfer in the same  
TXCLK cycle that TRDY is sampled low by the external controller. Again, the  
external controller must hold the last valid word on TXDATA[15:0] until TRDY is  
sampled high. In this case, that data is D2, the last word of the packet. The  
FREEDM-84A672 may drive TRDY low for an indeterminate number of TXCLK  
cycles. During this time, the external controller must wait and is not permitted to  
begin another burst data transfer until TRDY is sampled high. When the external  
controller samples TRDY high, the current burst transfer is deemed to be  
complete and the external controller may begin the next data transfer. The  
FREEDM-84A672 tristates the TRDY signal one TXCLK cycle after it has been  
driven high.  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
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