欢迎访问ic37.com |
会员登录 免费注册
发布采购

PM7385 参数 Datasheet PDF下载

PM7385图片预览
型号: PM7385
PDF下载: 下载PDF文件 查看货源
内容描述: 84 LINK , 672通道帧引擎和数据链路管理与ANY -PHY分组接口 [84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER WITH ANY-PHY PACKET INTERFACE]
分类和应用:
文件页数/大小: 244 页 / 2231 K
品牌: PMC [ PMC-SIERRA, INC ]
 浏览型号PM7385的Datasheet PDF文件第219页浏览型号PM7385的Datasheet PDF文件第220页浏览型号PM7385的Datasheet PDF文件第221页浏览型号PM7385的Datasheet PDF文件第222页浏览型号PM7385的Datasheet PDF文件第224页浏览型号PM7385的Datasheet PDF文件第225页浏览型号PM7385的Datasheet PDF文件第226页浏览型号PM7385的Datasheet PDF文件第227页  
PM7385 FREEDM-84A672  
DATA SHEET  
PMC-1990114  
ISSUE 6  
84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER  
WITH ANY-PHY PACKET INTERFACE  
Figure 19 – Receive APPI Timing (Boundary Condition)  
RXCLK  
RXADDR[2:0]  
RPA  
Dev 0  
NULL  
Dev 7  
Dev 0  
NULL  
Dev 6  
Dev 7  
NULL  
Dev 4  
Dev 6  
NULL  
Dev 4  
Dev 7  
Dev 1  
NULL  
Dev 7  
Dev 3  
Dev 1  
NULL  
Dev 2  
Dev 3  
NULL  
Dev 2  
RENB  
Dev 7  
D8  
RXDATA[15:0]  
RVAL  
CH 2  
D0  
D1  
D2  
D3  
CH 1  
D9  
RSX  
REOP  
RMOD  
RERR  
Figure 19 shows the boundary condition where a packet transfer completes  
shortly after the external controller has set RENB high to pause the FREEDM-  
84A672 device. The second data transfer is the final two words of a packet for  
FREEDM-84A672 device 7, channel 1.  
When FREEDM-84A672 device 0 places D2 on RXDATA[15:0], the external  
controller sets RENB high to pause the FREEDM-84A672 device. In the  
following RXCLK cycle, the FREEDM-84A672 provides D3 on RXDATA[15:0] and  
sets REOP high to conclude packet transfer. The external controller samples  
REOP high while RENB is high and recognizes that the packet transfer is  
complete. The external controller now knows that it doesn’t need to reselect  
FREEDM-84A672 device 0, but can select another FREEDM-84A672 device  
sharing the Rx APPI. The external controller decides to select FREEDM-84A672  
device 7 by placing this address on the RXADDR[2:0] signals. The external  
controller sets RENB low to commence data transfer from FREEDM-84A672  
device 7.  
12.6 Transmit APPI Timing  
The transmit Any-PHY packet interface (APPI) timing is shown in Figure 20. An  
external controller provides data to the FREEDM-84A672 device using the  
transmit APPI. The following discussion surrounding the transmit APPI functional  
timing assumes that multiple FREEDM-84A672 devices share a single external  
controller. The three most significant bits of TXADDR[12:0] perform device  
selection for purposes of polling while the ten least significant bits provide the  
channel poll address. All Tx APPI signals are shared between the FREEDM-  
84A672 devices.  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
214