PM7385 FREEDM-84A672
DATA SHEET
PMC-1990114
ISSUE 6
84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
WITH ANY-PHY PACKET INTERFACE
Figure 14 – Receive Link Timing
RCLK[n]
B1 B2 B3 B4 X B5 X
X X B6 B7 B8 B1 X
RD[n]
12.4 Transmit Link Timing
The timing relationship of the transmit clock (TCLK[n]) and data (TD[n]) signals is
shown in Figure 15. The transmit data is viewed as a contiguous serial stream.
There is no concept of time-slots or framing. Every eight bits are grouped
together into a byte with arbitrary byte alignment. Octet data is transmitted from
most significant bit (B1 in Figure 15) and ending with the least significant bit (B8
in Figure 15). Bits are updated on the falling edge of TCLK[n]. A transmit link
may be stalled by holding the corresponding TCLK[n] quiescent. In Figure 15,
bits B5 and B2 are shown to be stalled for one cycle while bit B6 is shown to be
stalled for three cycles. In Figure 15, the quiescent period is shown to be a low
level on TCLK[n]. A high level, effected by extending the high phase of the
previous valid bit, is also acceptable. Gapping of TCLK[n] can occur arbitrarily
without regard to byte nor frame boundaries.
Figure 15 – Transmit Link Timing
TCLK[n]
B1 B2 B3 B4 B5
B6
B7 B8 B1 B2
TD[n]
12.5 Receive APPI Timing
The receive Any-PHY packet interface (APPI) timing is shown in Figure 16
through Figure 19. The FREEDM-84A672 device provides data to an external
controller using the receive APPI. The following discussion surrounding the
receive APPI functional timing assumes that multiple FREEDM-84A672 devices
share a single external controller. All Rx APPI signals are shared between the
FREEDM-84A672 devices.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
210
PMC [ PMC-SIERRA, INC ]
