PM7385 FREEDM-84A672
DATA SHEET
PMC-1990114
ISSUE 6
84 LINK, 672 CHANNEL FRAME ENGINE AND DATA LINK MANAGER
WITH ANY-PHY PACKET INTERFACE
Figure 20 – Transmit APPI Timing (Normal Transfer)
TXCLK
TRDY
Dev 4
D129
TXDATA[15:0]
TSX
CH 0
D0
D1
D2
D126
D127
CH 0
D128
D130
D131
D132
D254
D255
TEOP
TMOD
TERR
Figure 20 shows transfer of a 256 word packet on the Tx APPI of FREEDM-
84A672 device 4, channel 0. The maximum burst data transfer (excluding
channel address prepend) is 128 words, so two data transfers are required to
complete the transfer of the 256 word packet.
The start of all burst data transfers is qualified with the TSX signal and an in-band
channel address on TXDATA[15:0] to associate the data to follow with a HDLC
channel. The TEOP signal indicates the end of valid packet data. The TMOD
and TERR signals held low except at the end of a packet (TEOP set high).
The FREEDM-84A672 starts driving the TRDY signal one TXCLK cycle after TSX
is sampled high. Upon sampling the TRDY signal high, the external controller
completes the current burst data transfer. The FREEDM-84A672 tristates the
TRDY signal one TXCLK cycle after it has been driven high. This is the case for
the first burst data transfer in Figure 20. In the second burst data transfer, the
FREEDM-84A672 drives the TRDY signal low to indicate that the FIFOs in the
TAPI672 are full and no further data may be transferred. Upon sampling the
TRDY signal low, the external controller must hold the last valid word of data on
TXDATA[15:0]. The FREEDM-84A672 may drive TRDY low for an indeterminate
number of TXCLK cycles. During this time, the external controller must wait and
is not permitted to begin another burst data transfer until TRDY is sampled high.
When the TAPI672 has at least one empty FIFO, the FREEDM-84A672 drives
the TRDY signal high. Upon sampling the TRDY signal high, the external
controller completes the current burst data transfer. The FREEDM-84A672
tristates the TRDY signal one TXCLK cycle after it has been driven high.
The external controller must sample the TRDY signal high before it can begin the
next burst data transfer. This prevents the external controller from bombarding
the FREEDM-84A672 device with small packets and allows the FREEDM-
84A672 to perform the necessary house-keeping and clean-up associated with
the ending of burst data transfers. This protocol also ensures that transitions
between burst data transfers do not require any extra per channel storage,
thereby simplifying implementation of both the external controller and the
FREEDM-84A672 device. Figure 21 illustrates this condition.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
215
PMC [ PMC-SIERRA, INC ]
