RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
Pin Name
Type
Pin
No.
Function
WRB
Input
D11
The write strobe signal (WRB) qualifies write
accesses to the FREEDM-32A256 device.
When CSB is set low, the D[15:0] bus contents
are clocked into the addressed register on the
rising edge of WRB.
RDB
Input
A11
The read strobe signal (RDB) qualifies read
accesses to the FREEDM-32A256 device.
When CSB is set low, the FREEDM-32A256
device drives the D[15:0] bus with the contents
of the addressed register on the falling edge of
RDB.
CSB
Input
C11
B11
The chip select signal (CSB) qualifies read/write
accesses to the FREEDM-32A256 device. The
CSB signal must be set low during read and
write accesses. When CSB is set high, the
microprocessor interface signals are ignored by
the FREEDM-32A256 device.
If CSB is not required (register accesses
controlled only by WRB and RDB) then CSB
should be connected to an inverted version of
the RSTB signal.
The interrupt signal (INTB) indicates that an
interrupt source is active and unmasked. When
INTB is set low, the FREEDM-32A256 device
has an active interrupt that is unmasked. When
INTB is tristate, no interrupts are active, or an
active interrupt is masked. Please refer to the
register description section of this document for
possible interrupt sources and masking.
INTB
Open-
Drain
Output
It is the responsibility of the external
microprocessor to read the status registers in
the FREEDM-32A256 device to determine the
exact cause of the interrupt.
INTB is an open drain output.
PROPRIETARY AND CONFIDENTIAL
36
PMC [ PMC-SIERRA, INC ]
