RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
Table 3 – Microprocessor Interface Signals (31)
Pin Name
Type
Pin
No.
Function
D[0]
I/O
A2
C3
A3
B3
C4
D5
A4
B4
C5
A5
C6
A6
B6
A7
D7
B7
The bi-directional data signals (D[15:0]) provide
a data bus to allow the FREEDM-32A256 device
to interface to an external micro-processor.
Both read and write transactions are supported.
The microprocessor interface is used to
configure and monitor the FREEDM-32A256
device.
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
D[8]
D[9]
D[10]
D[11]
D[12]
D[13]
D[14]
D[15]
A[2]
A[3]
A[4]
A[5]
A[6]
A[7]
A[8]
A[9]
A[10]
A[11]
Input
Input
C7
A8
The address signals (A[11:2]) provide an
address bus to allow the FREEDM-32A256
device to interface to an external micro-
processor. All microprocessor accessible
registers are dword aligned.
B8
C8
A9
D9
B9
C9
A10
B10
ALE
C10
The address latch enable signal (ALE) latches
the A[11:2] signals during the address phase of
a bus transaction. When ALE is set high, the
address latches are transparent. When ALE is
set low, the address latches hold the address
provided on A[11:2].
ALE has an integral pull-up resistor.
PROPRIETARY AND CONFIDENTIAL
35
PMC [ PMC-SIERRA, INC ]
