RELEASED
PM7383 FREEDM-32A256
DATASHEET
PMC-2010336
ISSUE 1
FRAME ENGINE AND DATA LINK MANAGER 32A256
Pin Name
Type
Input
Pin
No.
U20
Function
TMV8DC
The transmit 8.192 Mbps H-MVIP data clock
signal (TMV8DC) provides the transmit data
clock for links configured to operate in 8.192
Mbps H-MVIP mode.
TMV8DC is used to update data on TD[4m]
(0?m?7) when link 4m is configured for
8.192 Mbps H-MVIP operation. TMV8DC is
nominally a 50% duty cycle clock with a
frequency of 16.384 MHz.
TMV8DC is unused and should be tied low
when no physical links are configured for
operation in 8.192 Mbps H-MVIP mode.
TBD
Input
Y5
The transmit BERT data signal (TBD)
contains the transmit bit error rate test data.
When the TBERTEN bit in the BERT Control
register is set high, the data on TBD is
transmitted on the selected one of the
transmit data signals (TD[31:0]). TBD is
sampled on the rising edge of TBCLK.
BERT is not supported for H-MVIP links.
TBCLK
Tristate
Output
AA4
The transmit BERT clock signal (TBCLK)
contains the transmit bit error rate test clock.
TBCLK is a buffered version of the selected
one of the transmit clock signals
(TCLK[31:0]). TBCLK may be tristated by
setting the TBEN bit in the FREEDM-
32A256 Master BERT Control register low.
BERT is not supported for H-MVIP links.
PROPRIETARY AND CONFIDENTIAL
22
PMC [ PMC-SIERRA, INC ]
