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PM7380 参数 Datasheet PDF下载

PM7380图片预览
型号: PM7380
PDF下载: 下载PDF文件 查看货源
内容描述: 帧引擎和数据链路管理32P672 [FRAME ENGINE AND DATA LINK MANAGER 32P672]
分类和应用:
文件页数/大小: 332 页 / 2479 K
品牌: PMC [ PMC-SIERRA, INC ]
 浏览型号PM7380的Datasheet PDF文件第111页浏览型号PM7380的Datasheet PDF文件第112页浏览型号PM7380的Datasheet PDF文件第113页浏览型号PM7380的Datasheet PDF文件第114页浏览型号PM7380的Datasheet PDF文件第116页浏览型号PM7380的Datasheet PDF文件第117页浏览型号PM7380的Datasheet PDF文件第118页浏览型号PM7380的Datasheet PDF文件第119页  
RELEASED  
PM7380 FREEDM-32P672  
DATA SHEET  
PMC-1990262  
ISSUE 5  
FRAME ENGINE AND DATA LINK MANAGER 32P672  
1. Each of RD[15:12] has been sampled low and sampled high by rising  
edges of the corresponding RCLK[15:12] inputs, or  
2. Each of RD[15:12] has been sampled low and sampled high by rising  
edges of the RMVCK[1] input, or  
3. RD[12] has been sampled low and sampled high by rising edges of the  
RMV8DC input.  
RLGA[3] is set low when this register is read.  
RLGA[4]:  
The receive link group #4 active bit (RLGA[4]) monitors for transitions on the  
RD[19:16] and RCLK[19:16]/RMVCK[2]/RMV8DC inputs. RLGA[4] is set high  
when either:  
1. Each of RD[19:16] has been sampled low and sampled high by rising  
edges of the corresponding RCLK[19:16] inputs, or  
2. Each of RD[19:16] has been sampled low and sampled high by rising  
edges of the RMVCK[2] input, or  
3. RD[16] has been sampled low and sampled high by rising edges of the  
RMV8DC input.  
RLGA[4] is set low when this register is read.  
RLGA[5]:  
The receive link group #5 active bit (RLGA[5]) monitors for transitions on the  
RD[23:20] and RCLK[23:20]/RMVCK[2]/RMV8DC inputs. RLGA[5] is set high  
when either:  
1. Each of RD[23:20] has been sampled low and sampled high by rising  
edges of the corresponding RCLK[23:20] inputs, or  
2. Each of RD[23:20] has been sampled low and sampled high by rising  
edges of the RMVCK[2] input, or  
3. RD[20] has been sampled low and sampled high by rising edges of the  
RMV8DC input.  
RLGA[5] is set low when this register is read.  
RLGA[6]:  
The receive link group #6 active bit (RLGA[6]) monitors for transitions on the  
RD[27:24] and RCLK[27:24]/RMVCK[3]/RMV8DC inputs. RLGA[6] is set high  
when either:  
1. Each of RD[27:24] has been sampled low and sampled high by rising  
edges of the corresponding RCLK[27:24] inputs, or  
2. Each of RD[27:24] has been sampled low and sampled high by rising  
edges of the RMVCK[3] input, or  
3. RD[24] has been sampled low and sampled high by rising edges of the  
RMV8DC input.  
RLGA[6] is set low when this register is read.  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
104  
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