RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
implemented. However, when all four byte enables are negated, no access is
made to this register.
RLGA[0]:
The receive link group #0 active bit (RLGA[0]) monitors for transitions on the
RD[3:0] and RCLK[3:0]/RMVCK[0]/RMV8DC inputs. RLGA[0] is set high
when either:
1. Each of RD[3:0] has been sampled low and sampled high by rising
edges of the corresponding RCLK[3:0] inputs, or
2. Each of RD[3:0] has been sampled low and sampled high by rising
edges of the RMVCK[0] input, or
3. RD[0] has been sampled low and sampled high by rising edges of the
RMV8DC input.
RLGA[0] is set low when this register is read.
RLGA[1]:
The receive link group #1 active bit (RLGA[1]) monitors for transitions on the
RD[7:4] and RCLK[7:4]/RMVCK[0]/RMV8DC inputs. RLGA[1] is set high
when either:
1. Each of RD[7:4] has been sampled low and sampled high by rising
edges of the corresponding RCLK[7:4] inputs, or
2. Each of RD[7:4] has been sampled low and sampled high by rising
edges of the RMVCK[0] input, or
3. RD[4] has been sampled low and sampled high by rising edges of the
RMV8DC input.
RLGA[1] is set low when this register is read.
RLGA[2]:
The receive link group #2 active bit (RLGA[2]) monitors for transitions on the
RD[11:8] and RCLK[11:8]/RMVCK[1]/RMV8DC inputs. RLGA[2] is set high
when either:
1. Each of RD[11:8] has been sampled low and sampled high by rising
edges of the corresponding RCLK[11:8] inputs, or
2. Each of RD[11:8] has been sampled low and sampled high by rising
edges of the RMVCK[1] input, or
3. RD[8] has been sampled low and sampled high by rising edges of the
RMV8DC input.
RLGA[2] is set low when this register is read.
RLGA[3]:
The receive link group #3 active bit (RLGA[3]) monitors for transitions on the
RD[15:12] and RCLK[15:12]/RMVCK[1]/RMV8DC inputs. RLGA[3] is set high
when either:
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
103
PMC [ PMC-SIERRA, INC ]
