RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
Register 0x014 : FREEDM-32P672 Master Line Loopback #1
Bit
Type
Function
Default
Bit 31
to
Unused
XXXXH
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LLBEN[15]
LLBEN[14]
LLBEN[13]
LLBEN[12]
LLBEN[11]
LLBEN[10]
LLBEN[9]
LLBEN[8]
LLBEN[7]
LLBEN[6]
LLBEN[5]
LLBEN[4]
LLBEN[3]
LLBEN[2]
LLBEN[1]
LLBEN[0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
This register controls line loopback for links #0 to #15.
Note
This register is not byte addressable. Writing to this register modifies all the bits
in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
implemented. However, when all four byte enables are negated, no access is
made to this register.
LLBEN[15:0]:
The line loopback enable bits (LLBEN[15:0]) controls line loopback for
links #15 to #0. When links #0 through #15 are configured for channelised
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
107
PMC [ PMC-SIERRA, INC ]
