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PM7380 参数 Datasheet PDF下载

PM7380图片预览
型号: PM7380
PDF下载: 下载PDF文件 查看货源
内容描述: 帧引擎和数据链路管理32P672 [FRAME ENGINE AND DATA LINK MANAGER 32P672]
分类和应用:
文件页数/大小: 332 页 / 2479 K
品牌: PMC [ PMC-SIERRA, INC ]
 浏览型号PM7380的Datasheet PDF文件第113页浏览型号PM7380的Datasheet PDF文件第114页浏览型号PM7380的Datasheet PDF文件第115页浏览型号PM7380的Datasheet PDF文件第116页浏览型号PM7380的Datasheet PDF文件第118页浏览型号PM7380的Datasheet PDF文件第119页浏览型号PM7380的Datasheet PDF文件第120页浏览型号PM7380的Datasheet PDF文件第121页  
RELEASED  
PM7380 FREEDM-32P672  
DATA SHEET  
PMC-1990262  
ISSUE 5  
FRAME ENGINE AND DATA LINK MANAGER 32P672  
TLGA[4]:  
The transmit link group #4 active bit (TLGA[4]) monitors for low to high  
transitions on the TCLK[19:16] inputs. TLGA[4] is set high when rising edges  
have been observed on all four TCLK[19:16] inputs, and is set low when this  
register is read.  
TLGA[5]:  
The transmit link group #5 active bit (TLGA[5]) monitors for low to high  
transitions on the TCLK[23:20] inputs. TLGA[5] is set high when rising edges  
have been observed on all four TCLK[23:20] inputs, and is set low when this  
register is read.  
TLGA[6]:  
The transmit link group #6 active bit (TLGA[6]) monitors for low to high  
transitions on the TCLK[27:24] inputs. TLGA[6] is set high when rising edges  
have been observed on all four TCLK[27:24] inputs, and is set low when this  
register is read.  
TLGA[7]:  
The transmit link group #7 active bit (TLGA[7]) monitors for low to high  
transitions on the TCLK[31:28] & TMV8DC inputs. TLGA[7] is set high when  
either:  
1. Rising edges have been observed on all four TCLK[31:28] inputs, or  
2. A rising edge has been observed on the TMV8DC input.  
TLGA[7] is set low when this register is read.  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
106  
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