RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
implemented. However, when all four byte enables are negated, no access is
made to this register.
SYSCLKA:
The system clock active bit (SYSCLKA) monitors for low to high transitions on
the SYSCLK input. SYSCLKA is set high on a rising edge of SYSCLK, and is
set low when this register is read.
TBDA:
The transmit BERT data active bit (TBDA) monitors for low to high transitions
on the TBD input. TBDA is set high on a rising edge of TDB, and is set low
when this register is read.
RFP8A:
The receive 8.192 Mbps H-MVIP frame pulse activity bit (RFP8A) monitors for
low to high transitions on the RFP8B input. RFP8A is set high when RFP8B
has been sampled low and sampled high by falling edges of the RMV8FPC,
and is set low when this register is read.
TFP8A:
The transmit 8.192 Mbps H-MVIP frame pulse activity bit (TFP8A) monitors
for low to high transitions on the TFP8B input. TFP8A is set high when
TFP8B has been sampled low and sampled high by falling edges of the
TMV8FPC, and is set low when this register is read.
RFPA[3:0]:
The receive frame pulse activity bits (RFPA[3:0]) monitor for low to high
transitions on the RFPB[3:0] inputs. RFPA[n] is set high when RFPB[n] has
been sampled low and sampled high by falling edges of the corresponding
RMVCK[n], and is set low when this register is read.
TFPA[3:0]:
The transmit frame pulse activity bits (TFPA[3:0]) monitor for low to high
transitions on the TFPB[3:0] inputs. TFPA[n] is set high when TFPB[n] has
been sampled low and sampled high by falling edges of the corresponding
TMVCK[n], and is set low when this register is read.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
101
PMC [ PMC-SIERRA, INC ]
