RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
Register 0x00C : FREEDM-32P672 Master Clock / Frame Pulse / BERT
Activity Monitor and Accumulation Trigger
Bit
Type
Function
Default
Bit 31
to
Unused
XXXXXH
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
R
R
R
R
R
R
R
R
R
R
R
TFPA[3]
TFPA[2]
TFPA[1]
TFPA[0]
RFPA[3]
RFPA[2]
RFPA[1]
RFPA[0]
TFP8A
X
X
X
X
X
X
X
X
X
X
X
X
RFP8A
TBDA
SYSCLKA
This register provides activity monitoring on FREEDM-32P672 system clock,
H-MVIP frame pulse and BERT port inputs. When a monitored input makes a
transition, the corresponding register bit is set high. The bit will remain high until
this register is read, at which point, all the bits in this register are cleared. A lack
of transitions is indicated by the corresponding register bit reading low. This
register should be read periodically to detect for stuck at conditions.
Writing to this register delimits the accumulation intervals in the PMON
accumulation registers. Counts accumulated in those registers are transferred to
holding registers where they can be read. The counters themselves are then
cleared to begin accumulating events for a new accumulation interval. The bits
in this register are not affected by write accesses.
Note
This register is not byte addressable. Reading this register clears all the activity
bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
100
PMC [ PMC-SIERRA, INC ]
