RELEASED
PM7380 FREEDM-32P672
DATA SHEET
PMC-1990262
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
Register 0x010 : FREEDM-32P672 Master Link Activity Monitor
Bit
Type
Function
Default
Bit 31
to
Unused
XXXXH
Bit 16
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
TLGA[7]
TLGA[6]
TLGA[5]
TLGA[4]
TLGA[3]
TLGA[2]
TLGA[1]
TLGA[0]
RLGA[7]
RLGA[6]
RLGA[5]
RLGA[4]
RLGA[3]
RLGA[2]
RLGA[1]
RLGA[0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
This register provides activity monitoring on FREEDM-32P672 receive and
transmit link inputs. When a monitored input makes a low to high transition, the
corresponding register bit is set high. The bit will remain high until this register is
read, at which point, all the bits in this register are cleared. A lack of transitions
is indicated by the corresponding register bit reading low. This register should be
read periodically to detect for stuck at conditions.
Note
This register is not byte addressable. Reading this register clears all the activity
bits in the register. Byte selection using byte enable signals (CBEB[3:0]) are not
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
102
PMC [ PMC-SIERRA, INC ]
