RELEASED
PM7351 S/UNI-VORTEX
DATA SHEET
PMC-1980582
ISSUE 5
OCTAL SERIAL LINK MULTIPLEXER
• LVDS link and S/UNI-VORTEX identifiers are added to each cell (along with
the PHY identifier already added by S/UNI-DUPLEX) for use by ATM layer to
identify the cell source.
• Back-pressure sent to far end to prevent overflow of receiver FIFO.
LVDS TRANSMIT DIRECTION
• Per PHY and microprocessor port back-pressure used on each of the 8 links
to prevent overflow of downstream buffers.
• Device polling: provides Utopia-like TCA status for 264 PHYs (includes 8
control channels) based on back-pressure from the LVDS links.
• Cell transfer: Bus master adds a PHY address to each cell via a 12 bit
identifier. S/UNI-Vortex decodes and accepts cells for its links based on
software configured base addresses.
PARALLEL BUS INTERFACE:
• Both directions: 16 bit wide, 50 MHz max clock rate, bus slave.
• Cells transferred to the bus: Utopia L2 compatible with optional expanded
length cells. Appears as single PHY, with a cell prepend identifying the
source PHY ID of each cell. Alternatively, Utopia L2 compliance is supported
by placing the PHY ID inside the UDF/HEC fields of a standard ATM cell.
• Cells received from the bus: The Any-PHY bus is similar to Utopia L2 but with
optional expanded length cells and expanded addressing capabilities. The
S/UNI-VORTEX appears to the bus master as a 264 port multi-PHY device (8
links, each with 32 PHYs & communication channel). PHY address is added
as cell prepend or optionally in HEC/UDF field when standard length cells are
desired.
MICROPROCESSOR INTERFACE
• 8 bit data bus, 8 bit address bus.
• Provides read/write access to all configuration and status registers.
• Provides CRC32 calculation and cell transfer registers to support an
embedded microprocessor to microprocessor communication channel
over the LVDS link.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
11
PMC [ PMC-SIERRA, INC ]
