RELEASED
PM7351 S/UNI-VORTEX
DATA SHEET
PMC-1980582
ISSUE 5
OCTAL SERIAL LINK MULTIPLEXER
Ball
Ball
Type No. Function
Name
REFCLK
Input AB13 The reference clock input (REFCLK) must provide a
jitter-free reference clock. It is used as the reference
clock by both clock recovery and clock synthesis
circuits. Any jitter below 1 MHz is transferred directly
to the TXDn+/- outputs. The high speed serial
interface bit rate is eight times the REFCLK frequency.
RES
Analog P4
P3
A 4.75kΩ ±1% resistor must be connected between
these two balls to achieve the correct LVDS output
signal levels.
RESK
ATP0
ATP1
Analog K3 The Analog Test Points (ATP) are provided for
K4 production test purposes. In mission mode they are
high impedance and should be connected to ground.
TX8K
Input J23 The transmit 8 kHz timing reference (TX8K) input
allows a traceable signal to be transmitted to the far
end of the high-speed serial links via TXD0+/- through
TXD7+/-. A rising edge on TX8K is encoded in the
next cell transmitted.
Although TX8K is targeted at a typical need of
transporting an 8 kHz signal, its frequency is not
constrained to 8 kHz. Any frequency less than the cell
rate is permissible.
RX8K
Output A14 The receive 8 kHz timing reference (RX8K) output
presents the timing extracted from one of the receive
high-speed serial links.
The rising edge of RX8K is accurate to the nearest
byte boundary of the high-speed serial link; therefore,
a small amount of jitter is present. At a link rate of
155.52 Mb/s, the jitter is 63ns peak-to-peak.
Pulses on RX8K are always 16 high-speed serial link
bit periods wide (two REFCLK periods).
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
14
PMC [ PMC-SIERRA, INC ]
