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PM7351-BGI 参数 Datasheet PDF下载

PM7351-BGI图片预览
型号: PM7351-BGI
PDF下载: 下载PDF文件 查看货源
内容描述: [Support Circuit, 1-Func, CMOS, PBGA304, 31 X 31 MM, 1.51 MM HEIGHT, 1.27 MM PITCH, SBGA-304]
分类和应用: ATM异步传输模式电信电信集成电路
文件页数/大小: 174 页 / 1840 K
品牌: PMC [ PMC-SIERRA, INC ]
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RELEASED  
PM7351 S/UNI-VORTEX  
DATA SHEET  
PMC-1980582  
ISSUE 5  
OCTAL SERIAL LINK MULTIPLEXER  
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DESCRIPTION  
The PM7351 S/UNI-VORTEX is a monolithic integrated circuit typically used with  
its sister device, the S/UNI-DUPLEX, to implement a point-to-point serial  
backplane interconnect architecture.  
Up to sixteen S/UNI-VORTEX devices can reside on a common cell processing  
card along side a traffic management device. The traffic management device  
exchanges cells with the S/UNI-VORTEX via 16-bit SCI-PHY or Any-PHY  
interfaces. Flow control is effected across this interface via cell available signals  
generated by the S/UNI-VORTEX. In the downstream direction, the availability  
of a buffer for each logical channel can be polled by the traffic management  
device. In the upstream direction, an indication is provided whether there is one  
or more cells queued in the S/UNI-VORTEX for transfer.  
Each S/UNI-VORTEX can be connected to eight line cards via 100 to 200 Mb/s  
serial links. Each upstream link has its own queue. If a queue becomes nearly  
full, a flow control indication is sent downstream. In the downstream direction,  
each logical channel has a dedicated cell buffer to avoid head of line blocking.  
The serialization of cells from the cell buffers is throttled by flow control  
information sent from the line card via the upstream high-speed link.  
A microprocessor port provides access to internal configuration and monitoring  
registers. The port may also be used to insert and extract cells in support of a  
control channel.  
LVDS INTERFACES, BOTH DIRECTIONS  
8 independent 4-wire LVDS serial transceivers each operating at up to 200  
Mbps across PCB or backplane traces, or across up to 10 meters of 4-wire  
twisted pair cabling for inter-shelf communications.  
Usable bandwidth (excludes system overhead) of 186 Mbps per direction per  
LVDS link.  
Full integrated LVDS clock synthesis and recovery. No external analog  
components are required.  
LVDS RECEIVE DIRECTION  
Weighted round robin multiplex of cell streams from the 8 LVDS links into a  
single cell stream which is transferred to the parallel bus under control of the  
bus master.  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
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