RELEASED
PM7351 S/UNI-VORTEX
DATA SHEET
PMC-1980582
ISSUE 5
OCTAL SERIAL LINK MULTIPLEXER
Fig. 2 Three Stage Multiplex Architecture
Line Card #1
Modem
S/UNI-
Modem
Modem
DUPLEX
Line Card #2
Modem
Modem
Modem
S/UNI-
VORTEX
S/UNI-
DUPLEX
Policing
OA&M
Buffering
Discard
WAN
S/UNI-
OA&M
up-link
Scheduling
VORTEX
WAN Card
Line Card #N
Modem
Modem
Modem
S/UNI-
DUPLEX
Stage 1
Stage 2
Stage 3
The first stage resides on the line card and spans only those ports physically
terminated by that card. Since it is confined to a single card, this first stage of
multiplexing readily lends itself to a simple parallel bus based multiplex topology.
The second stage of concentration occurs between the core card(s) and the line
cards, including line cards that are on a separate shelf. This second stage is
best served by a redundant serial point-to-point technology. The third stage of
multiplexing is optional and resides on the core card. This third stage is used in
systems with a large number of line cards that require several S/UNI-VORTEX
devices to terminate the second stage of aggregation. Since the third stage of
aggregation is confined to the core card, it lends itself readily to a parallel bus
implementation. This three stage approach is implemented directly by the
S/UNI-VORTEX and its sister device, the S/UNI-DUPLEX.
The S/UNI-DUPLEX acts as the line card’s bus master. It implements the first
stage of multiplexing by routing traffic from the PHYs and transmitting the traffic
simultaneously over two high speed (up to 200 Mbps) serial 4-wire LVDS links.
One serial link attaches to the active core card, the other to the standby core
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
7
PMC [ PMC-SIERRA, INC ]
