RELEASED
PM7351 S/UNI-VORTEX
DATA SHEET
PMC-1980582
ISSUE 5
OCTAL SERIAL LINK MULTIPLEXER
Ball
Ball
Type No. Function
Name
Upstream (Receive) Bus
RANYPHY
Input C15 The Receive Any-PHY configuration input determines
the protocol of the upstream cell interface.
If RANYPHY is logic low, the interface complies to the
SCI-PHY specification. As such, all outputs have a
single cycle latency.
If RANYPHY is logic high, the interface complies to
the Any-PHY specification. Relative to SCI-PHY, all
outputs have an additional cycle of latency.
RANYPHY is an asynchronous input and is expected
to be held static.
RCLK
RPA
Input D17 The Receive FIFO clock (RCLK) is used to read words
from the S/UNI-VORTEX upstream cell buffer. RCLK
must cycle at a 52 MHz or lower instantaneous rate.
RSOP, RPA, RPRTY and RDAT[15:0] are updated on
the rising edge of RCLK. RENB and RADR[4:0] are
sampled on the rising edge of RCLK.
Output C18 The RPA signal indicates whether at least one cell is
queued for transfer.
Upon sampling a RADR[4:0] value that equals the
value on VADR[4:0], the S/UNI-VORTEX drives the
RPA with the cell availability status immediately if
RANYPHY is logic low. If RANYPHY is logic high,
RPA has an additional cycle of latency. RPA will be a
one if at least one entire cell is available.
RPA is high-impedance when not polled.
RPA is updated on the rising edge of RCLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
15
PMC [ PMC-SIERRA, INC ]
