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PM7350-PGI 参数 Datasheet PDF下载

PM7350-PGI图片预览
型号: PM7350-PGI
PDF下载: 下载PDF文件 查看货源
内容描述: [Support Circuit, 1-Func, CMOS, PBGA160, 15 X 15 MM, 1.81 MM HEIGHT, PLASTIC, BGA-160]
分类和应用: ATM异步传输模式电信电信集成电路
文件页数/大小: 245 页 / 898 K
品牌: PMC [ PMC-SIERRA, INC ]
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RELEASED  
PM7350 S/UNI DUPLEX  
DATA SHEET  
PMC-1980581  
ISSUE 8  
DUAL SERIAL LINK PHY MULTIPLEXER  
Ball  
Name  
Ball  
No. Function  
Type  
High Speed LVDS Links  
TRSTB  
Input  
A13 The active-low test reset (TRSTB) signal provides  
an asynchronous S/UNI-DUPLEX test access port  
reset via the IEEE P1149.1 test access port.  
TRSTB is a Schmitt triggered input with an integral  
pull-up resistor.  
Note that when not being used, TRSTB must be  
connected to the RSTB input.  
Power and Ground  
BIAS  
VDD  
Power  
Power  
A7 When tied to +5V, the BIAS input is used to bias the  
wells in the input and I/O pads so that the pads can  
tolerate 5V on their inputs without forward biasing  
internal ESD protection devices. When tied to  
+3.3V, the inputs and bi-directional inputs will only  
tolerate 3.3V level inputs.  
B3 The digital power (VDD) pins should be connected  
C5 to a well-decoupled +3.3 V DC supply.  
C13  
D10  
E2  
E14  
F3  
K1  
L1  
L4  
L9  
M7  
M12  
N3  
N13  
P6  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
43  
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