RELEASED
PM7350 S/UNI DUPLEX
DATA SHEET
PMC-1980581
ISSUE 8
DUAL SERIAL LINK PHY MULTIPLEXER
9
FUNCTIONAL DESCRIPTION
The S/UNI-DUPLEX supports two distinct methods of interconnection to
modems, PHYs and other ATM devices: via a parallel bus interface or via 16
clocked serial data interface. In either case the primary function of the S/UNI-
DUPLEX is to transfer cells between the external devices and the high speed
LVDS serial links. At far end of the LVDS link another S/UNI-DUPLEX device or
a S/UNI-VORTEX device must be connected. See the PMC-Sierra Data Sheet
for the PM7351 S/UNI-VORTEX for details on that device.
In the LVDS transmit direction, cells are read from the external devices and
multiplexed onto the LVDS link. Flow control, alarm, PHY identification, and
other control information is added to each cell to ensure a managed link is
maintained.
In the LVDS receive direction, system overhead is stripped off each cell before it
is sent to the appropriate device on the parallel bus or over the clocked serial
data interfaces. In bus slave mode, the PHY ID is left in the cell, typically for use
by an ATM layer device such as PMC-Sierra’s S/UNI-ATLAS so that the cell
source can be determined. In bus master mode, or in clocked serial interface
mode the PHY ID is stripped off and used to direct the cell to the appropriate
Utopia slave device or to the appropriate clocked serial interface.
For a discussion of overall system architecture issues, the reader is referred to a
companion document provided by PMC-Sierra titled S/UNI-VORTEX & S/UNI-
DUPLEX TECHNICAL OVERVIEW. The document number is PMC-981025 and
it can be obtained by one of the various means described on the last page of this
document.
The remainder of this section focuses on the interfaces and functionality of a
single S/UNI-DUPLEX device, although the reader should also view things in the
context of the attached far-end device (either a S/UNI-DUPLEX or a S/UNI-
VORTEX).
9.1 Parallel Bus Interface
The S/UNI-DUPLEX’s parallel interface. is selected when the SCIANY input is
tied high. This interface supports three types of bus: Utopia Level 2, SCI-PHY
Level 2, and Any-PHY.
Table 1 provides the correspondence between the S/UNI-DUPLEX pin names
and the Utopia Level 2, SCI-PHY Level 2 and Any-PHY signals. The Any-PHY
bus format is enabled when the IANYPHY and OANYPHY inputs are tied high,
SCI-PHY or Utopia is selected when the inputs are tied low. Input and output bus
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
47
PMC [ PMC-SIERRA, INC ]
