RELEASED
PM7350 S/UNI DUPLEX
DATA SHEET
PMC-1980581
ISSUE 8
DUAL SERIAL LINK PHY MULTIPLEXER
Ball
Name
Ball
No. Function
Type
High Speed LVDS Links
RAVD
RAVS
TAVD
TAVS
GND
Analog
Power
J11 The power (RAVD) pin for the LVDS receivers. This
pin should be connected to analog +3.3V. It should
be electrically isolated (as much as possible) from
the other power connections.
Analog
Ground
J12 The ground (RAVS) pin for the LVDS receivers. This
pin should be connected to analog GND. It should
be electrically isolated (as much as possible) from
the other ground connections.
Analog G11 The power (TAVD) pins for the LVDS transmitters.
Power
K11 These pins should be connected to analog +3.3V.
These should be electrically isolated (as much as
possible) from the other power connections.
Analog H12 The ground (TAVS) pins for the LVDS transmitters.
Ground K12 These pins should be connected to analog GND.
These should be electrically isolated (as much as
possible) from the other ground connections.
Thermal G7 The Thermal Vias (GND) are used to improve
Vias
G8 thermal conductance of the device package. They
H7 should be connected to the PCB ground plane. The
H8 GND pins are not electrically connected to the other
ground pins of the package.
Notes on Pin Description:
1. All S/UNI-DUPLEX inputs and bi-directionals present minimum capacitive
loading and operate at TTL logic levels, except RXD1+/- and RXD2+/-.
2. Inputs RSTB, ALE, TMS, TDI and TRSTB have internal pull-up resistors.
3. The recommended power supply sequencing is as follows:
3.1 During power-up, the voltage on the BIAS pin must be kept equal to or
greater than the voltage on the VDD pins, to avoid damage to the
device.
3.2 The VDD power must be applied before input pins are driven or the input
current per pin be limited to less than the maximum DC input current
specification (20 mA).
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
45
PMC [ PMC-SIERRA, INC ]
