RELEASED
PM7350 S/UNI DUPLEX
DATA SHEET
PMC-1980581
ISSUE 8
DUAL SERIAL LINK PHY MULTIPLEXER
Ball
Name
Ball
No. Function
Type
High Speed LVDS Links
RDB
Input
A8 The active-low read enable (RDB) signal is low
during S/UNI-DUPLEX register read accesses. The
S/UNI-DUPLEX drives the D[7:0] bus with the
contents of the addressed register while RDB and
CSB are low.
WRB
Input
I/O
D9 The active-low write strobe (WRB) signal is low
during S/UNI-DUPLEX register write accesses. The
D[7:0] bus contents are clocked into the addressed
register on the rising WRB edge while CSB is low.
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
C14 The bi-directional data bus D[7:0] is used during
D13 S/UNI-DUPLEX register read and write accesses.
D12
D14
F11
F13
F12
F14
A[7]/TRS
A[6]
A[5]
Input
C9 The address bus A[7:0] selects specific registers
A9 during S/UNI-DUPLEX register accesses.
B9
A[4]
A[3]
A[2]
A[1]
B10 The test register select (TRS) signal selects
D11 between normal and test mode register accesses.
A11 TRS is high during test mode register accesses,
C11 and is low during normal mode register accesses.
B11
A[0]
RSTB
ALE
Input
Input
A10 The active-low reset (RSTB) signal provides an
asynchronous S/UNI-DUPLEX reset. RSTB is a
Schmitt triggered input with an integral pull-up
resistor.
B8 The address latch enable (ALE) is active-high and
latches the address bus A[5:0] when low. When
ALE is high, the internal address latches are
transparent. It allows the S/UNI-DUPLEX to
interface to a multiplexed address/data bus. ALE
has an integral pull-up resistor.
All address pins are latched.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
41
PMC [ PMC-SIERRA, INC ]
