RELEASED
PM7350 S/UNI DUPLEX
DATA SHEET
PMC-1980581
ISSUE 8
DUAL SERIAL LINK PHY MULTIPLEXER
Fig. 22 SCI-PHY Interface, Output Bus Master Transfer Timing
OFCLK
OADDR[4:0]
OAVALID
OENB
A
IFh
B
IFh
A
1Fh
B
1Fh
C
1Fh
D
CH A
W 49
OCA
ODAT[15:0]
OSOC
W 48
W 50
W 51
W 52
XXX
W 0
W 1
W 2
W 3
W 4
W 5
Fig. 23 is an example of the functional timing of the SCI-PHY/Any-PHY Interface
when configured as a 16-bit Any-PHY compliant output bus slave. In this
example, address “A” (since the Output Address Match register is 5 bit wide, the
most significant bit is ignored) corresponds to the content of the Output Address
Match register of the S/UNI-DUPLEX. In this example, OAVALID is used as the
OADDR[5] line. OAVALID has to be logic low for a match to occur. The SCI-
PHY/Any-PHY output interface acts a proxy for its 32 logical channels. Once it
returns a logic high on OCA in response to a poll, a cell may be transferred.
Coincident with the OSX output, the logical channel ID is output as the first word
of the cell, its most significant bits derived from the contents of the Extended
Address Match registers. The OENB input is not required to be deasserted at the
end of a cell transfer. Upon completion of the cell transfer, the interface
autonomously deselects itself.
The transfer can be paused by deasserting OENB. The cell transfer from the
same logical channel resumes immediately when OENB is reasserted low.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
209
PMC [ PMC-SIERRA, INC ]
