RELEASED
PM7350 S/UNI DUPLEX
DATA SHEET
PMC-1980581
ISSUE 8
DUAL SERIAL LINK PHY MULTIPLEXER
Fig. 21 SCI-PHY Interface, Output Bus Slave Transfer Timing
OFCLK
1Fh
A
IFh
A
IFh
A
IFh
B
IFh
C
IFh
D
OADDR[4:0]
OAVALID
OENB
OCA
W 48
W 49
W 50
W51
W 52
W 53
CH ID
W 0
W 1
ODAT[15:0]
OPRTY
OSOC
Fig. 22 is an example of the functional timing of the SCI-PHY/Any-PHY Interface
when configured as a 8-bit Utopia Level 2 compliant output bus master. The
S/UNI-DUPLEX polls PHY devices round robin with OADDR[4:0] and OAVALID
while performing a cell transfer. The PHY at address “A” responds to polling by
asserting OCA high. Because of internal processing delays of the S/UNI-
DUPLEX interface, the polling process stops only after the address of next PHY
of the round robin sequence is set on the bus. IADDR[4:0] value is reverted to
the preceding polled PHY address until the cell transfer is completed. The
S/UNI-DUPLEX selects PHY “A” for a cell transfer and resumes the round robin
polling process.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
208
PMC [ PMC-SIERRA, INC ]
