RELEASED
PM7350 S/UNI DUPLEX
DATA SHEET
PMC-1980581
ISSUE 8
DUAL SERIAL LINK PHY MULTIPLEXER
Register 0x80: Master Test
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Reserved
PMCATST
PMCTST
DBCTRL
IOTST
X
0
R/W
W
X
X
X
0
W
W
R/W
W
HIZDATA
HIZIO
X
0
R/W
This register is used to enable S/UNI-DUPLEX test features. All bits, except
PMCTST and PMCATST, are reset to zero by a reset or a software reset of the
S/UNI-DUPLEX.
HIZIO, HIZDATA:
The HIZIO and HIZDATA bits control the tri-state modes of the S/UNI-
DUPLEX. While the HIZIO bit is a logic one, all output pins of the S/UNI-
DUPLEX except the data bus and output TDO are held tri-state. The
microprocessor interface is still active. While the HIZDATA bit is a logic one,
the data bus is also held in a high-impedance state which inhibits
microprocessor read cycles. The HIZDATA bit is overridden by the DBCTRL
bit.
IOTST:
The IOTST bit is used to allow normal microprocessor access to the test
registers and control the test mode in each TSB block in the S/UNI-DUPLEX
for board level testing. When IOTST is a logic one, all blocks are held in test
mode.
DBCTRL:
The DBCTRL bit is used to pass control of the data bus drivers to the CSB
pin. When the DBCTRL bit is set to logic one and either IOTST or PMCTST
are logic one, the CSB pin controls the output enable for the data bus. While
the DBCTRL bit is set, holding the CSB pin high causes the S/UNI-DUPLEX
to drive the data bus and holding the CSB pin low tri-states the data bus. The
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
173
PMC [ PMC-SIERRA, INC ]
