RELEASED
PM7350 S/UNI DUPLEX
DATA SHEET
PMC-1980581
ISSUE 8
DUAL SERIAL LINK PHY MULTIPLEXER
11.1.1 128x8 RAM
The following procedure tests the six 128x8 RAMs simultaneously:
1. Hold REFCLK, TCK and TX8K low.
2. Set the RESET bit of the Master Reset and Identity register (0x00) to logic
1 to place the device in a known state.
3. Write the following register locations to select the test mode and initialize
the BIST circuitry:
1. Write 0x02 to 0xB1, 0xB5, 0xB9
2. Write 0x01 to 0xB0, 0xB4, 0xB8
3. Write 0x55 to 0xB2, 0xB6, 0xBA
These registers do not have default values and must be written.
4. Clear the RESET bit of the Master Reset and Identity register (0x00) to
logic 0.
5. Set the IOTST bit of the Master Test register (0x80) to logic 1. This
activates the BIST test mode.
6. Start toggling the REFCLK, TCK and TX8K inputs at up to a maximum
frequency of 4 MHz. All clocks need be phase and frequency locked.
7. After exactly 2045 clock cycles read the following registers and compare
against the expected data. Any discrepancies represent a test failure.
The two bits being compared are flags that are cleared when at least one
RAM bit location returns an incorrect value. Letting the test run indefinitely
simply causes the test sequences to be repeated.
Expected
D[7:0]
A[7:0]
0xB2, 0xB6, 0xBA
xxxx0011
11.1.2 2048x8 RAM
The following procedure tests the two 2048x8 RAMs: simultaneously:
1. Hold REFCLK and TCK low.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
176
PMC [ PMC-SIERRA, INC ]
