RELEASED
PM7350 S/UNI DUPLEX
DATA SHEET
PMC-1980581
ISSUE 8
DUAL SERIAL LINK PHY MULTIPLEXER
Register 0x71:Transmit Serial Indirect Channel Data
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
DHCS
HSCR
0
0
DSCR
0
Unused
Unused
Unused
Unused
Unused
X
X
X
X
X
This register contains data read from the channel provision RAM of the Transmit
Clocked Serial Data Interface after an indirect channel read operation or data to
be inserted into the channel provision RAM in an indirect channel write operation.
DSCR:
The indirect scrambling disable bit (DSCR) configures scrambling. The
scramble disable bit to be written to the channel provision RAM, in an indirect
channel write operation, must be set up in this register before triggering the
write. When DSCR is logic 1, scrambling is disabled. When DSCR is logic 0,
either the 48 byte payload or the entire bit stream (if HSCR is logic 1) is
scrambled. DSCR reflects the value written until the completion of a
subsequent indirect channel read operation.
HSCR:
The indirect header scrambling enable bit (HSCR) configures header
scrambling. The header scramble enable bit to be written to the channel
provision RAM, in an indirect channel write operation, must be set up in this
register before triggering the write. When HSCR is logic 1 and DSCR is logic
0, the header is scrambled in addition to the payload. When HSCR is logic 0
and DSCR is logic 0, only the cell payload is scrambled. HSCR reflects the
value written until the completion of a subsequent indirect channel read
operation.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
169
PMC [ PMC-SIERRA, INC ]
