RELEASED
PM7350 S/UNI DUPLEX
DATA SHEET
PMC-1980581
ISSUE 8
DUAL SERIAL LINK PHY MULTIPLEXER
Register 0x6D: Receive Serial LCD Count Threshold
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LCDC[7]
LCDC[6]
LCDC[5]
LCDC[4]
LCDC[3]
LCDC[2]
LCDC[1]
LCDC[0]
0
1
1
0
1
0
0
0
LCDC[7:0]:
The LCDC[7:0] bits represent the number of consecutive cell periods the
receive cell processor of the Clock Serial Data Interface must be out of cell
delineation before loss of cell delineation (LCD) is declared. Likewise, LCD is
not deasserted until the receive cell processor is in cell delineation for the
number of cell periods specified by LCDC[7:0].
The default value of LCD[7:0] of 104 translates to 73 ms at 600 kb/s.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
167
PMC [ PMC-SIERRA, INC ]
