RELEASED
PM7350 S/UNI DUPLEX
DATA SHEET
PMC-1980581
ISSUE 8
DUAL SERIAL LINK PHY MULTIPLEXER
Register 0x6B:
Receive Serial Indirect Channel Interrupt and Status
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
R
OOCDV
LCDV
X
X
X
X
X
X
X
X
Unused
Unused
OOCDI
HCSI
R
R
R
R
FOVRI
LCDI
This register contains data read from the channel provision RAM of the Receive
Clocked Serial Data Interface after an indirect read operation.
LCDI:
The LCDI bit is set to logic 1 when there is a change in the loss of cell
delineation (LCD) state. This bit is reset immediately after a read to this
register.
FOVRI:
The FOVRI bit is set to logic 1 when a FIFO overrun has occurred or is about
to occur. Normally the occurrence of the FOVRI interrupt indicates that one
or more user cells have been discarded due to the buffer overflow condition.
However, if the overflow pending condition exists only temporarily (and when
only IDLE cells are being received) it is possible that no user cells were
actually discarded. This bit is reset immediately after a read to this register.
HCSI:
The HCSI bit is set to logic 1 when an HCS error is detected. This bit is reset
immediately after a read to this register.
OOCDI:
The OOCDI bit is set to logic 1 when the logical channel enters or exits the
SYNC state. The OOCDV bit indicates whether the logical channel is in the
SYNC state or not. The OOCDI bit is reset immediately after a read to this
register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
164
PMC [ PMC-SIERRA, INC ]
